Testing architecture of circuits integrated on a wafer

ABSTRACT

A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure TEG realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional application from U.S. patent application Ser. No. for 13/554,133 filed Jul. 20, 2012, which claims priority to Italian Patent Application No. MI2011A001418, filed Jul. 28, 2011, the disclosures of which are hereby incorporated.

TECHNICAL FIELD

The disclosure relates to a testing architecture of integrated circuits on a wafer. More particularly, but not exclusively, the disclosure relates to an architecture of integrated circuits on a wafer of the type comprising structures TEG realized in scribe lines providing separation between these integrated circuits, and the following description is made with reference to this field of application for convenience of explanation only.

BACKGROUND

As it is well known, for the electric selection of devices carried out on wafer, i.e., the so called testing EWS (acronym of “Electrical-Wafer-Sorting”), it is typically necessary to electrically couple a tester or ATE (acronym of “Automated Test Equipment”) that executes measures on a wafer whereon there are electronic components to be tested or selected or evaluated, in particular integrated circuits or chips. A terminal portion of the testing apparatus is schematically shown in FIG. 1A, globally indicated with 1.

The interface between the real tester ATE 1A and a wafer 6 includes a plurality of devices to be tested or selected, in particular chips 7 (also indicated as integrated circuits or IC, acronym of “Integrated Circuit”) is a so called probe card 2, which is a board including in substance a PCB (acronym of “Printed Circuit Board”) and a probe head 3 that in turn includes different e.g., hundreds or thousands) of probes 4 that electrically couple the tester ATE 1A to all, or almost all, the contact pads 8 of a chip 7 to be tested, as shown in greater detail in FIG. 1B. In particular, each end portion or tip 9 of the probes 4 comes into contact with a contact pad 8 of the chip 7 during a testing phase.

In general, the wafer 6 groups a plurality of chips 7 to be tested, and during the testing steps it is put on a support called chuck 5, shown in the portion of the testing apparatus 1, and belonging to an apparatus also called prober (not shown in the figure), this support 5 being thus also indicated as a prober chuck.

The number of contact pads 8 necessary for a determined testing may be smaller or equal to the total number of contact pads 8 of the chip 7 to be tested.

One may test in a similar way even if the chips 7 have contact bumps instead of contact pads 8.

Before each chip 7 is encapsulated in a corresponding package, it is known to execute the testing of the chip 7 itself, being still on the wafer 6, using the probes 4 that are directly coupled to the contact pads 8, and that thus execute the so called probing of the contact pad 8 they come in contact with.

After the testing, the wafer 6 is cut (a process referred to as “singulation”) and the chips 7 that have been tested and are determined to be properly operating are assembled in their package, ready for further process steps, also including final test steps of the chips 7 in the package wherein they have been assembled.

To this purpose, on the wafer 6, between one chip 7 and another, an area called a scribe line SL is created within which a saw or a laser will pass during the cutting or singulation operation, necessary for separating the various devices being on the wafer for executing the various assembling and encapsulating or packaging steps of the same devices, as schematically shown in FIG. 2. In particular, in the schematic enlargement indicated by way of illustration in FIG. 2, a group of four chips 7, indicated as IC A, IC B, IC C and IC D, are separated by a first scribe line SL1, in particular with a horizontal orientation according to the local reference of the figure, and a second scribe line SL2, in particular with a vertical orientation in the local reference of the figure.

Moreover, as shown in this figure, in the scribe lines (in particular in the first scribe line SL1) elementary structures are sometimes introduced, usually indicated as structures TEG (acronym of “Test Element Group”), these structures being used, for example, for the testing of some process parameters, that are in general measured before the electric wafer test EWS.

The structures TEG are, in general, coupled to pads being also in the scribe line SL and normally distinct with respect to the pads of the chip 7.

It is also known from U.S. Pat. No. 7,224,176, which is incorporated by reference, to realize a wafer wherein the pads of the structures TEG coincide with the pads of the chips.

In practice, however, such a realization has problems in the operation since the structures TEG thus coupled suffer from the effect of the circuits being in the chips and from their faults. In particular, there may be problems tied to leakage currents in the chip or in the pads shared by chips and structures TEG that may be, for example, in short circuit with the ground.

Furthermore, in the case in which the structures TEG are used for understanding the manufacturing process problems of the wafer, it may be difficult to execute reliable and accurate measures by using pads shared by chips and structures TEG, due to the presence of defects in the chip itself on the wafer due to the process problems.

The circuits realized on the chips also introduce parasitics (e.g., resistances, capacitances, non-linear effects, etc.) that may jeopardize the accuracy of the measurement on the structures TEG.

Furthermore, each chip 7 is surrounded by a conventional protection structure, the so called seal ring 7A.

More in particular, the seal ring 7A has the aim of sealing the respective chip 7 and mechanically strengthening it for ensuring the reliability and protection against the mechanical effort exercised by the saw during the cutting or singulation of the chip 7 from the wafer 6.

The seal ring 7A is usually placed between an area where the contact pads of the chip itself are placed, normally indicated as pad ring, and the scribe line confining with the chip itself.

Usually, the seal ring 7A includes a plurality of metal layers and of vias that couple them so as to realize a structure able to block also ions and polluting substances (such as for example humidity) that could jeopardize the good operation of the chip 7 after the singulation.

Different implementations are known for the realization of a seal ring of an integrated electronic device or chip. For example, in U.S. Pat. No. 6,300,223, which is incorporated by reference, a structure of a seal ring is described wherein dielectric layers and metal layers are alternated, the structure being also provided with a trench for reducing the mechanical stresses at the singulation of the chips from the wafer. Other structures suitable for realizing a seal ring are also known from U.S. Pat. Nos. 7,605,448 and 6,492,716, which are incorporated by reference.

For avoiding the problems of radiofrequency interferences being able to jeopardize the operation of the chip, it is also known to suitably cut the seal ring in those points whereat substrate disturbances could be injected coming from internal circuits of the chip itself (such as power amplifiers, clock signals generators, processing circuits of input/output digital signals, etc).

The growing requests for electronic applications able to sustain higher and higher temperatures have also brought the introduction of new materials for realizing the pads and the couplings between the pads and the package of the chips so as to ensure a good electric coupling.

Some of these materials are also used for strengthening the pad itself. For example, it is possible to use surface covering layers realized in materials with greater hardness with respect to those traditionally used, such as for example aluminum, avoiding in this way breaking the possible microelectronic structures being under the pad.

A pad made of some layers of different materials able to improve the strength of the pad as a whole is described for example in United States Patent Application Publication No. 2005/0073057, which is incorporated by reference.

In this case, a generic pad 8 of a chip includes for example an upper metal layer corresponding to a final metal layer of the chip wherein this pad is realized and made of a generic material A (for example copper). According to the teaching of United States Patent Application Publication No. 2005/0073057, above the material A there is presented a first material B having a high hardness (for example nickel or an alloy thereof) and a second material C (for example palladium or an alloy thereof). Possibly, another layer of a further material D (for example gold or an alloy thereof) may be realized above the second material C, the pad being also surrounded by a passivation layer E, as schematically shown in FIG. 3 of the present patent application.

Between the materials A and B, as well as between the materials B and C and between the materials C and D, there may possibly be also layers of still other materials, created one above the other using known techniques in the field of the manufacturing of integrated circuits.

For example, one of the known techniques for the growth of these materials is the so called electroless process, the considerations that follow being however valid also for other types of processes.

In particular, further to the growth and/or deposition of the materials according to the process used, these same materials will be present on all the pads 8 of the wafer 6, and in particular on the pads of the chips 7 but also on the pads of the structures TEG.

After the testing of these structures TEG and of the chips 7 of the wafer, the wafer itself is cut and the working devices are assembled in a package.

The presence of the hard materials on the pads of the structures TEG makes it however difficult to execute the cut or singulation of the chips 7 from the wafer 6, executed as already said by means of a diamond saw, for example. In this case in fact, the saw may damage the edge of the chip 7 exactly because of the presence of hard materials on the pads of the structures TEG, thus creating chippings.

Solutions currently known do not allow then to execute measures in an accurate and reliable way of the structures TEG. In particular, these measures are not reliable in the case of shared pads by the structures TEG and the chips 7 that surround them. Further problems introduced by the presence of the seal ring, that requires the use of complex structures aimed at crossing it, that contribute to the increase of the final costs of the chips thus obtained. Finally, the presence of hard materials aimed at strengthening the structures of the pad also on the surface of the pads of the structures TEG introduces problems of chipping of the chip at their singulation from the wafer wherein they have been realized.

SUMMARY

An embodiment is an architecture of a semiconductor wafer including a plurality of chips separated by suitable scribe lines wherein structures TEG are realized, this architecture having such structural and functional characteristics as to allow to overcome the limits and the drawbacks still affecting the architectures realized according to the prior art.

An embodiment is realizing at least one testing architecture provided with a switching circuitry for acting on the circuits inside the integrated circuits on the wafer, but also on those of the structures TEG realized in the scribe lines.

An embodiment is a testing architecture of integrated circuits on a wafer of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit characterized in that it includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuits and by the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

More in particular, an embodiment includes the following supplementary and optional characteristics, taken alone or in combination, when needed.

According to an embodiment, the at least one pad may belong to a group of pads arranged in at least one of these first and second integrated circuit in correspondence with the scribe line.

According to another embodiment, the at least one pad may be a coupling pad between the first and second circuits and the switching circuitry may include at least one first and one second switch that couple the coupling pad with the first and second circuits respectively.

According to yet another embodiment, the testing architecture may further include at least one enable pad coupled to the switching circuitry.

In particular, the enable pad may be shared by the first and second integrated circuits and coupled to control terminals of the first and second switches.

Furthermore, the testing architecture may include respective enable pads in the first and second integrated circuits, coupled to control terminals of the first and second switches.

According to another embodiment, the testing architecture may include at least one dedicated pad coupled only to one of these first and second circuits.

Moreover, the switching circuitry may further included couplings of the fuse link type with the first circuit.

According to an embodiment, the switching circuitry may also include test circuits associated with at least one of these first and second circuits.

In particular, these test circuits may be of the BIST type (Built-In Self Test).

According to another embodiment, the testing architecture may further include a support circuit realized in at least one of the integrated circuits and coupled to the switching circuitry.

Suitably, the switching circuitry may include at least one further switch coupled to the support circuitry and to the first circuit.

In particular, this further switch may have a control terminal coupled to the at least one enable pad.

According to yet another embodiment, the testing architecture may further include at least one controller realized in the scribe line and coupled to the first circuit, this controller being suitable for supervising the testing of the first circuit.

In this case, the switching circuitry may include at least one further switch coupled between the controller and at least one further coupling pad of the first and second integrated circuits.

In particular, this further switch may have a control terminal coupled to the at least one enable pad.

According to an embodiment, the testing architecture for an integrated circuit provided with a seal ring realized by means of a conductive structure that is formed by a plurality of conductive lines and extends in a peripheral portion of the integrated circuit next to the scribe line on different planes starting from a substrate, is characterized in that it is reinforced by at least one pillar structure formed by the coupling of further conductive lines to realize the at least one pad.

According to this embodiment, the at least one pillar structure may include conductive couplings that develop perpendicularly to the planes and couple the further conductive lines arranged on different but contiguous planes.

In particular, the pillar structure may include at least one upper conductive line emerging from the integrated circuit through an opening.

According to an embodiment, the seal ring may include a linear element that crosses a structure of the at least one pad, passing near the at least one pillar structure below the upper conductive line.

Moreover, the integrated circuit may include suitably doped areas realized in the substrate so as to extend substantially in correspondence with the at least one pillar structure.

In particular, these areas may be suitably doped in a complementary way with respect to the substrate so as to form inversely biased junctions PN.

According to another embodiment, the testing architecture may include a coupling line that extends in the scribe line and/or at least one line of coupling to the circuitry realized in the integrated circuit.

According to yet another embodiment, the testing architecture may include at least one conductive via of coupling of a metal line of a structure TEG with the conductive line that extends in the scribe line, this conductive via realizing a fragile-making point at a successive singulation step of the integrated circuit from the wafer wherein it is realized.

In particular, the pad and the coupling lines may be insulated from the seal ring, this pad having a substantially ring-like shape that surrounds the seal ring.

Furthermore, according to an embodiment, the testing architecture may include fuse links developed in parallel to the seal ring.

According to another embodiment, the integrated circuit may include at least one first well realized in the substrate and doped in an opposite way with respect to it, the coupling lines being coupled to the well and the seal ring being insulated therefrom.

Finally, the integrated circuit may include at least one second well realized in the substrate and doped in a similar way to it, the seal ring being coupled to the second well.

BRIEF DESCRIPTION OF THE DRAWINGS

Characteristics and advantages of the testing architecture for integrated circuits on wafer will be apparent from the following description of embodiments thereof given by way of indicative and non-limiting example with reference to the annexed drawings.

In these drawings:

FIGS. 1A and 1B respectively show, schematically and in greater detail, a conventional terminal portion of a testing apparatus of integrated circuits on wafer;

FIG. 2 schematically shows a conventional wafer including a plurality of integrated circuits (chips) separated by scribe lines;

FIG. 3 schematically shows a conventional multilayer pad;

FIG. 4 schematically shows an embodiment of a testing architecture of integrated circuits on wafer;

FIG. 5 schematically shows an embodiment of the architecture of FIG. 4;

FIGS. 6-8 schematically show other embodiments of the architecture of FIG. 4;

FIG. 9 schematically shows another embodiment of the architecture of FIG. 4;

FIGS. 10-11 schematically show further embodiments of the architecture of FIG. 4;

FIG. 12 shows a diagram relative to the architecture of FIG. 4;

FIGS. 13A-13B schematically show portions of a conventional seal ring;

FIG. 13C schematically shows the section of an embodiment of a pillar included in an embodiment of the architecture;

FIGS. 14A and 14B schematically show an embodiment of a pad of an integrated circuit provided with a seal ring to be used in an embodiment of the architecture of FIG. 4;

FIG. 15 schematically shows an integrated circuit provided with pad and seal ring as shown in FIGS. 14A and 14B and to be used in an embodiment of the architecture of FIG. 4;

FIGS. 16, 17A, 17B, 18 and 19 schematically show details and embodiments of the pad and of the seal ring of FIGS. 14A and 14B;

FIG. 20 schematically shows another embodiment of a pad of an integrated circuit provided with a seal ring to be used in an embodiment of the architecture of FIG. 4;

FIGS. 21, 22A, 22B and 23 schematically show embodiments and details of the pad and of the seal ring of FIG. 20.

DETAILED DESCRIPTION

With reference to these figures, and in particular to FIG. 4, a wafer 40 of semiconductor material is globally and schematically shown, in particular a portion thereof including at least one first and one second integrated circuit, 20A and 20B, separated by a scribe line 21.

It is to be noted that the figures are not drawn to scale, but are instead drawn so as to emphasize features of embodiments. Moreover, in the figures, the different pieces are shown in a schematic way, and their shape may vary according to the desired application.

Furthermore, elements or measures described for convenience of illustration with reference to an embodiment are not to be intended as limited thereto, the different characteristics, structures and/or elements having the possibility to be indifferently used in combination with the different embodiments described.

Each integrated circuit, 20A or 20B, includes a plurality of pads 24, usually arranged along its perimeter, as well as further inner circuitry that can be suitably tested. By way of simplicity, FIG. 4 indicates only a generic circuit, in particular inside the first integrated circuit 20A, hereafter indicated as circuit IC 25. Each integrated circuit is also enclosed by a seal ring 23 realized in its peripheral portion 22.

The wafer 40 also includes at least one structure TEG, in particular including at least one circuit realized in the scribe line 21, hereafter indicated as circuit TEG 35.

According to an embodiment, on the wafer 40 a testing architecture is realized, globally indicated with 50. In particular, this testing architecture 50 includes at least the structures TEG, as well as switching circuitry 30 realized in the integrated circuits 20A and 20B and in the scribe line 21 and including electronic switches, for example, including at least one transistor MOS. More in particular, the integrated circuits 20A and 20B include respective pads, indicated with 26A and 26B respectively, these pads being common between the circuit IC 25 and the circuit TEG 35, the switching circuitry 30 being coupled to the circuit IC 25, to the circuit TEG 35, and to the common pads, 26A and 26B. Although not shown in the figure for sake of simplicity, also the second integrated circuit 20B can include inner circuitry suitably coupled, by means of the switching circuitry 30, to the common pad 26B and thus to the circuit TEG 35.

It is to be noted how the group of the pads arranged along the scribe line 21 that separates the integrated circuits 20A and 20B, these groups of pads being indicated with 24A and 24B, respectively, as well as the circuit TEG 35 form an integrated circuit including the structures TEG, hereafter indicated as integrated circuit TEG 30A.

In substance, the testing architecture 50, thanks to the switching circuitry 30, is able to enable the integrated circuit TEG 30A or an integrated circuit 20A, 20B or both if tests are to be executed that involve both the integrated circuits, in a simple and flexible way.

More in particular, as schematically shown in FIG. 5, according to an embodiment, the testing architecture 50 includes a first and a second pad, 26A and 27A, as well as an enable pad 28A realized in the first integrated circuit 20A, in particular in correspondence with the group of pads 24A that faces the scribe line 21, as well as switching circuitry 30 formed by a first, a second, and a third switch, SW1, SW2, and SW3.

As shown in FIG. 5, the first switch SW1 couples the circuit IC 25 to the first pad 26A, the second switch SW2 couples the first pad 26A to the circuit TEG 35, and the third switch SW3 couples the circuit TEG 35 to the second pad 27A. Suitably, the three switches, SW1, SW2 and SW3, have control terminals coupled to the enable pad 28A.

In this way, an enable signal applied to the enable pad 28A of the testing architecture 50 is able to select the test enabling of the circuit IC 25 or of the circuit TEG 35, this enable signal opening and/or closing the switches SW1, SW2 and SW3 of the switching circuitry 30 according to the desired test condition. For example, for enabling the integrated circuit TEG 30A or an integrated circuit 20A, 20B the enable signal applied to pad 28A would have one state to close the switch SW2 (and open switch SW1) when testing the integrated circuit TEG 30A and another state to close the switch SW1 (and open switch SW2) when testing the circuit IC 25. Alternatively, when testing both, the enable signal applied to pad 28A may have one state to close both switches SW1 and SW2 and another state to open both switches.

According to an embodiment, a pad, in particular the second pad 27A, could be dedicated to the integrated circuit TEG 30A only, the same being not used for the integrated circuit, for example, the first integrated circuit 20A, as shown in FIG. 5.

These dedicated pads may be used, for example, for measures having particular requisites, like, for example, measures of the breakdown voltage of the structures TEG that normally require voltages of some tens of volts.

According to an alternative embodiment, the testing architecture 50 may include an enable pad for each integrated circuit 20A, 20B, in particular a first pad 26B and an enable pad 28B also in the second integrated circuit 20B, as schematically shown in FIG. 6.

In this case, the testing architecture 50 includes the first pad 26A realized in the first integrated circuit 20A and the switching circuitry 30 includes the first and second switches SW1 and SW2 that couple this first pad 26A to the circuit IC 25 and the circuit TEG 35, suitably driven thanks to the coupling of their control terminals to the enable pad 28A. Similarly, the testing architecture 50 includes a further coupling pad 26B realized in the second integrated circuit 20B, and the switching circuitry 30 includes a fourth and a fifth switch, SW4 and SW5, that couple this further pad 26B to a further circuit IC (not shown) and to the circuit TEG 35, also the fourth and fifth switches, SW4 and SW5, being suitably driven thanks to the coupling of their control terminals to a further enable pad 28B of the testing architecture 50.

In a similar way, according to a further embodiment, the testing architecture 50 may include only one enable pad, for example the enable pad 28A realized in the first integrated circuit 20A, for enabling more than one integrated circuit. In this case, as schematically shown in FIG. 7, the testing architecture 50 includes the first pad 26A in the first integrated circuit 20A, and the switching circuitry 30 includes the first and second switches SW1 and SW2 that couple this first pad 26A to the circuit IC 25 and the circuit TEG 35, suitably driven thanks to the coupling of their control terminals to the enable pad 28A. The testing architecture 50 includes a further coupling pad 26B in the second integrated circuit 20B, and the switching circuitry 30 includes a fourth and a fifth switch, SW4 and SW5, that couple this further pad 26B to a further circuit IC (not shown) and to the circuit TEG 35, suitably driven thanks to the coupling of their control terminals still to the enable pad 28A.

According to a further embodiment, the switching circuitry 30 of the testing architecture 50 also includes couplings of the fuse-link type. In particular, as schematically shown in FIG. 8, the testing architecture 50 includes in this case the first pad 26A realized in the first integrated circuit 20A and coupled to the circuit IC 25 by means of the first switch SW1 of the switching circuitry 30, that also includes a first fuse link FL1 that couples the first pad 26A to the circuit TEG 35. Similarly, the testing architecture 50 includes a further pad 26B realized in the second integrated circuit 20B and coupled by means of a switch SW5 of the switching circuitry 30 to a further circuit IC (not shown); the switching circuitry 30 also includes a second fuse link FL2 that couples the further pad 26B to the circuit TEG 35.

According to these embodiments, the tests on the circuits IC and on the circuits TEG are executed separately. In particular, if the test of the circuit TEG 35 is executed first and then the test of the circuit IC 25 is executed, it is possible to disable the coupling to the integrated circuits 20A and 20B by means of the enable pad 28A, to execute the measures on the circuit TEG 35, and then to execute the test on the circuit IC 25 eliminating the coupling between the pads, 26A and 26B, and the circuit TEG 35 by means of the fuse links FL1 and FL2.

It is to be noted that, in this case, by burning the fuse links FL1 and FL2 there will be also the possibility to avoid leakage currents after the cut or singulation of the wafer 40.

According to another embodiment, the testing architecture 50 includes test circuits associated with circuit IC 25 of the integrated circuits 20A and 20B, and/or the circuit TEG 35 of the scribe line 21. In particular, as schematically shown in FIG. 9, a test circuit IC 29 is realized in the first integrated circuit 20A and coupled to the circuit IC 25, and a test circuit TEG 31 is realized in the scribe line 21 and coupled to the circuit TEG 35. In an embodiment, the test circuits IC 29 and TEG 31 are of the BIST (Built-In Self Test) type.

Furthermore, according to an embodiment, schematically shown in FIG. 10, the testing architecture 50 may further include, for example in the first integrated circuit 20A, support circuitry 25′, suitably coupled to the circuit TEG 35. In particular, the support circuitry 25′ includes circuits that are in the first integrated circuit 20A that may be used also for the testing besides for the final application. This support circuitry 25′ is coupled to the circuit TEG 35 by means of a further switch SW6 being in the switching circuitry 30, suitably driven, for example, by the enable pad 28A.

This support circuitry 25′ may include, for example, an ADC converter (Analog to Digital Converter) and/or a DAC converter (Digital to Analog Converter), useful, for example, for executing analog measures by using an ATE with mainly digital resources. Alternatively, this support circuitry 25′ may include a communication interface.

Finally, according to an alternative embodiment, the testing architecture 50 may also include a controller 32 coupled to the circuit TEG 35 or, like in the example shown in FIG. 11, to the test circuit TEG 31. The controller 32 supervises the testing of the various circuits TEG 35 acting also on the switches of coupling to the pad of the circuit IC 25 being in the switching circuitry 30 for possibly using circuits inside the integrated circuit 20A or 20B itself for possibly executing at least one test.

In an alternative embodiment, the controller 32 (that may be also indicated as TEG Test Controller or more in general as Test Controller) may be possibly used also for executing at least one test of the circuits inside at least one of the integrated circuits 20A and 20B.

As shown by way of indication in the figure, the testing architecture 50 also includes further pads, in particular the pads 29A and 29B realized in the first and second integrated circuits, 20A and 20B, and coupled to the controller 32, by means of respective switches SW7 and SW8 realized in the switching circuitry 30. The controller 32 is also coupled to the test circuit TEG 31. Also the switches SW7 and SW8 are suitably driven, for example by the enable pad 28A. In the example of the figure, the first integrated circuit 20A also includes the support circuitry 25′ coupled, by means of the switch SW6, to the circuit TEG 35.

Thanks to the use of the controller 32 it is possible, for example, to execute the test of the circuits TEG 35 simultaneously to the test of the circuits IC 25.

In its more general form, schematically shown in FIG. 12, an embodiment relates to a wafer 40 including a plurality of integrated circuits, each including at least one inner circuit or circuit IC 25 to be tested. The wafer 40 also includes at least one testing architecture 50 in turn including at least one structure TEG realized in a scribe line providing separation between at least one pair of these integrated circuits, in turn including at least one inner circuit or circuit TEG 35.

According to an embodiment, the testing architecture 50 includes at least one switching circuit 30, coupled between the circuit IC 25 and/or the circuit TEG 35 and a plurality of pads 24 of the integrated circuits of the wafer 40. In particular, the switching circuitry 30 is coupled to the groups of pads 24A and 24B that form the integrated circuit TEG 30A, and more in particular to the pads, 26A, 26B, 27A, 27B and to the enable pads 28A, 28B.

The testing architecture 50 may also include test circuits for the integrated circuits and/or for the structures TEG. More in particular, as schematically shown in FIG. 12, the testing architecture 50 may include at least one test circuit IC 29 coupled to the circuit IC 25 and/or at least one test circuit TEG 31 coupled to the circuit TEG 35.

Furthermore, the testing architecture 50 may include a controller 32, coupled to the pads 24 by means of the switching circuitry 30.

The wafer 40 and/or the testing architecture 50 may further include inner circuitries, indicated with 25′ and 25″, that may be realized in the integrated circuits and/or in the scribe line and coupled in turn to the pads by means of the switching circuitry 30.

It is to be noted that, thanks to an embodiment of the testing architecture 50, at least one structure being in the scribe line may be used, also or exclusively, for the testing WLBI (Wafer Level Burn-In), in particular by using the pads of the integrated circuits coupled thereto for its suitable driving.

According to an embodiment, the integrated circuits 20A, 20B and also the integrated circuits TEG 30A may share structures and circuits, as well as have also their own dedicated circuits and structures, as explained in relation to the different embodiments previously described.

It is to be noted how the main shared structures of the testing architecture 50 concentrate: inside the area where the seal ring 23 is realized, which can also be crossed by coupling lines and around the pads 24.

It is known that the seal ring 23 may include a plurality of metal layers (metal layers) and vias that couple them so as to realize a structure able to block also ions and polluting substances (such as for example humidity) that could jeopardize the good operation of the integrated circuits after the singulation of the wafer 40.

In its most general form, the testing architecture 50 is realized for an integrated circuit 20 including at least one conductive structure that extends in a peripheral portion 22 thereof on different planes starting from a substrate 37 of the wafer 40 and realizes the seal ring 23.

In particular, in this peripheral portion 22 a plurality of conductive lines 33 are realized, in particular metal lines, arranged on different planes starting from the substrate 37 to form the seal ring 23 that surrounds the integrated circuit 20 itself, as schematically shown in FIG. 13A, the planes being substantially parallel to the substrate 37 and developing in perpendicular starting therefrom in a vertical direction, considering the local reference of FIG. 13A. In particular, by way of illustration, the words “horizontal” and “vertical” will be used hereafter in the description for indicating development directions parallel to the substrate and perpendicular thereto, respectively, without these words being intended to limit the disclosure in any way.

In an embodiment of the seal ring 23, conductive lines 33 belonging to different planes are suitably coupled to each other by means of conductive couplings 36, for example conductive vias, that develop perpendicularly to these planes. In this way, a seal ring 23 is obtained having a structure substantially similar to a wall, starting from the substrate 37, as schematically shown in FIG. 13B.

In particular, the seal ring 23 may be reinforced with pillar structures 34 shown in FIG. 13C that may be used to form a pad 24 for the integrated circuit 20 and for the testing architecture 50 associated therewith, as it will be described hereafter.

More in particular, as schematically shown in FIG. 14A, each structure 34 that realizes a pad 24 is formed by a plurality of conductive lines 43 formed in the different planes and intercoupled to each other by conductive couplings 46. Suitable vias 46′ are provided for the coupling to the substrate 37. In an alternative embodiment, not shown, the pillar structures 34 may be devoid of the vias 46′ for coupling to the substrate 37. It is noted how the coupling between the conductive lines 43 by means of conductive vias 46 that realize the pad 24 strengthen the structure as a whole. In particular, in the case shown in the figure, the pillar structure 34 is also provided with an upper conductive line 24A emerging from the integrated circuit 20 through an opening OP so as to realize the pad 24. In the case shown in the figure, a further plurality of conductive lines 33 coupled by conductive vias 36 realizes the seal ring 23 around the integrated circuit 20.

According to another embodiment, the seal ring 23 includes linear elements, as schematically shown in the FIGS. 14A, 14B, 15 and 16. In this case, the linear element of the seal ring 23 crosses the pillar structures 34 of the pad 24, in particular below the upper conductive lines 24A.

In FIG. 16 wells 38A and 38B are schematically shown that form junctions PN in the substrate 37 in correspondence with the pillar structures 34, these pillar structures 34 being coupled to each other by means of an upper conductive line 33 so as to realize the pad 24. Moreover, a further well 39 may be realized below the seal ring 23, in turn including wall structures formed by the further conductive lines 33 suitably intercoupled to each other and to the further well 39 by means of vertical conductive couplings or vias 36.

In this way it is possible to insulate the pad 24 from the substrate 37 thanks to the presence of the junctions PN realized by the wells 38A and 38B. These junctions could be used also as a protection diode against the electrostatic discharges (ESD). These wells 38A and 38B are suitably doped in a complementary way with respect to the substrate 37 so as to form inversely biased junctions PN, indicated with DsubA and DsubB in the figure. In the case, for example, of a substrate 37 of the P type, the wells 38A and 38B will be suitably of the N type and in the case of a substrate 37 of the N type, the wells 38A and 38B will be of the P type.

Furthermore, thanks to the presence of the further well 39 below the seal ring 23, the same will have the possibility to be coupled or not to the substrate 37 according to the application. In the figure the further well 39 is doped in a similar way with respect to the substrate 37 and with a high doping for increasing its conductivity.

It is thus evident that, in this embodiment, a part of the pad 24 is formed inside the area surrounded by the seal ring 23, while a part of the pad is outside.

It is to be noted the fact that it is possible to further provide the presence of a hard material on the surface of the pad 24, in particular on its upper conductive line 24A emerging from the opening OP. In substance, in this way a reinforced seal ring is obtained, having a similar shape as that of a castle with towers.

In another embodiment of the testing architecture 50, the pillar structures described for the generic pad 24 are used for realizing the coupling and/or enable pad of the testing architecture 50.

According to another embodiment, a pad 24 will possibly have at least suitable coupling lines between the inner and external parts of the pad with respect to the area delimited by the seal ring 23, in particular in the form of a first and a second coupling line, 43A and 43B. More in detail, the first coupling line 43A allows the coupling between the pad 24 and structures realized in the scribe line 21, for example structures TEG by means of a further metallization line 44A coupled to the first metallization line 43A by means of suitable vertical conductive couplings 45A, for example conductive vias, while the second coupling line 43B allows the coupling between the pad 24 and inner circuitry of the integrated circuit 20A. In this way, the pad thus realized may be used as a coupling pad of the testing architecture 50 according to an embodiment.

The pad 24 and the coupling lines 43A and 43B are insulated from the seal ring 23 itself, the pad 24 having a substantially ring-like shape that surrounds the seal ring 23.

In an alternative embodiment, not shown, if the pillar structures 34 are devoid of the coupling vias 46′ to the substrate 37, the losses towards the substrate will be reduced, and in particular the leakage currents.

According to an alternative embodiment, schematically shown in the FIGS. 17A and 17B, the pillar structures 34 may be coupled to each other by means of further lines 43C.

The pad 24 could be thus coupled to circuits external to the integrated circuit 20A in such a way to avoid damages of the pad 24 itself further to lateral mechanical efforts due to the cut or singulation of the wafer 40, and in this sense vertical conductive couplings 45A will be possibly present in the form of a via that, subjected to mechanical effort during this cutting step, is uncoupled from one of the two conductive lines 43A and/or 44A that couple these external structures, for example structures TEG, to the pad 24.

In a further alternative embodiment, schematically shown in FIG. 18, it is possible to couple these external structures, and in particular the further conductive line 44A, directly to the well 38B realized under the pad 24 in correspondence with the scribe line 21, in such a way to avoid the damage of the pad 24.

According to an embodiment, it is also possible to obtain a fuse link FL providing coupling between the pad 24 and external circuitry, if any, such as the structures TEG by simply tapering off a coupling line, in particular a metallization line, as shown in FIG. 19, this fuse link FL having a development being substantially parallel to the seal ring 23 so as to save space. This fuse link may be compressed in the testing architecture 50 according to an embodiment, in particular in its switching circuitry 30.

In a second embodiment of the seal ring 23, schematically shown in FIG. 20, the pads 24 are realized inside the seal ring 23 that surrounds the integrated circuit 20A in a traditional way.

According to an embodiment, for coupling the pad 24 to circuits external to the integrated circuit 20A, the seal ring 23 is crossed in a simple way by means of a well 38B doped in an opposite way with respect to the substrate 37, and in particular in the exemplifying case of a substrate of the P type, the well 38B will be of the N type. More in particular, this well 38B is not coupled to the seal ring 23, in turn formed by means of a plurality of conductive lines 33 intercoupled by means of vertical conductive couplings 36 in a wall-like structure, as schematically shown in FIG. 21. It is noted that the wall-like structure of the seal ring 23 allows to avoid the creation of contacts and/or vias that copule it to this well 38B, its lower vertical conductive couplings 36′, i.e. for the coupling to the substrate 37 indeed, being suitably absent in correspondence with this well 38B.

The seal ring 23 according to the application could be coupled to the substrate 37 or insulated therefrom thanks to the presence of the wells 39A and 39B, as shown in FIG. 21.

More in particular, as shown in FIGS. 22A and 22B, the integrated circuit 20 includes a wall-like structure of the seal ring 23 realized in correspondence with and in contact with the wells 39A and 39B, while the same is insulated from the well 38B, whereto, instead, the conductive lines 44A and 44B are coupled, by means of respective vertical conductive couplings 45A and 45B, for the coupling of the pad 24 or of the inner circuits of the integrated circuit 20A, respectively, to circuits external to the integrated circuit 20A, this coupling being realized by the well 38B. A view from above of the substrate including the wells 38B, 39A and 39B as well as at least one pad 24 is given by way of example in FIG. 23.

In conclusion, the testing architecture 50 of the integrated circuits on wafer realized according to an embodiment includes at least one switching circuitry and is able to execute the testing of the structures TEG in a reliable way, avoiding to put pads of high hardness materials in the scribe line providing separation between the integrated circuits of the wafer itself, these pads possibly introducing, as previously seen in relation to the prior art, problems during the cutting or singulation step of the wafer. In particular, according to an embodiment, the testing architecture allows to avoid the chipping of the integrated circuits further to the cut of the wafer, thus improving the quality of the final product.

In particular, according to an embodiment, the testing architecture allows to execute the testing of the structures TEG and of the integrated circuits realized on the wafer, so that the presence of the ones does not jeopardize the measures and the test on the others and vice versa. More in particular, the testing architecture according to an embodiment may also include at least one plurality of pads shared by at least one inner circuitry of the integrated circuits on the wafer and at least one circuitry relative to the structures TEG realized in the scribe line.

Further according to an embodiment, the testing circuitry embedded in the integrated circuits on the wafer is able to correctly operate when there is a protection seal ring realized around each of these integrated circuits.

According to an embodiment, the testing architecture as proposed allows to make the circuits inside the area delimited by the seal ring cooperate with circuits external of the same, so as to further simplify the test and measures executed on the integrated circuits of the wafer. These advantages are attained with simple modifications of the seal ring by adding pillar structures.

According to a further embodiment, thanks to the testing architecture, inside a same test flow it is possible to execute both the test EWS of the integrated circuits and the test of the structures TEG, besides possible structures for the testing WLBI.

An embodiment also allows to reinforce the seal ring. Furthermore, the scribe line being devoid of pads, it is possible, in case, to reduce the width of the scribe line itself in conformity with the requisites necessary for the cut of the wafer.

A first integrated circuit sliced from such a wafer per an embodiment above may be part of a system that includes at least one other integrated circuit coupled to the first integrated circuit. The integrated circuits may be disposed on a same die or on respective dies, and one of the integrated circuits may include a controller such as a processor.

From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. 

The invention claimed is:
 1. A method for wafer testing wherein a wafer includes a first integrated circuit die and a second integrated circuit die separated by a scribe line, said scribe line further including a testing circuit, and the wafer further including a first test pad in the first integrated circuit die electrically coupled to the testing circuit in the scribe line by a first switch element and a second test pad in the first integrated circuit die electrically coupled to a control terminal of the first switch element, the method comprising: coupling probes of a probe head to contact the first and second test pads; applying a control signal with a first logic state from the probe head to the second test pad to actuate the first switch element for connecting the first test pad to the testing circuit in the scribe line; applying a test signal to or receiving a test signal from the testing circuit in the scribe line through the probe of the probe head which is in contact with the first test pad; switching the first logic state of said control signal to a second logic state to deactuate the first switch element for disconnecting the first test pad from the testing circuit in the scribe line; and applying a further test signal to or receiving a further test signal from the first integrated circuit through the probe of the probe head which is in contact with the first test pad.
 2. The method of claim 1, further including a third test pad in the second integrated circuit die electrically coupled to the testing circuit in the scribe line by a second switch element, wherein the second test pad is electrically coupled to a control terminal of the second switch element, wherein applying the control signal from the probe head to the second test pad further actuates the second switch element for connecting the third test pad to the testing circuit in the scribe line, the method further comprising: applying an additional test signal to or receiving an additional test signal from the testing circuit in the scribe line through the probe of the probe head which is in contact with the third test pad.
 3. The method of claim 1, further including a third switch element electrically coupling the first test pad to internal circuitry of the first integrated circuit die, wherein the second test pad is electrically coupled to a control terminal of the third switch element, wherein switching the control signal further actuates the third switch element for connecting the first test pad to the internal circuitry of the first integrated circuit die in support of applying the further test signal to or receiving the further test signal from the internal circuitry of the first integrated circuit die through the probe of the probe head which is in contact with the first test pad.
 4. The method of claim 3, wherein applying a control signal further deactuates the third switch element for disconnecting the first test pad from the internal circuitry of the first integrated circuit die.
 5. A method for wafer testing wherein a wafer includes a first integrated circuit die and a second integrated circuit die separated by a scribe line, said scribe line further including a testing circuit, and the wafer further including a first test pad in the first integrated circuit die coupled to the testing circuit in the scribe line by a first switch element and a second test pad in the first integrated circuit die coupled to a control terminal of the first switch element, the method comprising: applying a control signal with a first logic state to the second test pad through a first test probe to actuate the first switch element and cause the first test pad to be electrically connected to the testing circuit in the scribe line; applying a test signal to or receiving a test signal from the testing circuit in the scribe line through a second test probe that is in contact with the first test pad; changing the first logic state of said control signal to a second logic state applied to the second test pad through a first test probe to deactuate the first switch element and cause the first test pad to be electrically disconnected from the testing circuit in the scribe line; and applying a further test signal to or receiving a further test signal from the first integrated circuit through the second test probe that is in contact with the first test pad.
 6. The method of claim 5, wherein the wafer further includes a third test pad in the second integrated circuit die coupled to the testing circuit in the scribe line by a second switch element, the method further comprising: actuating the second switch element to cause the third test pad to be electrically connected to the testing circuit; and applying an additional test signal to or receiving an additional test signal from the testing circuit in the scribe line through a third test probe that is in contact with the third test pad.
 7. The method of claim 6, wherein the second test pad in the first integrated circuit die is further electrically coupled to a control terminal of the second switch element and wherein actuating the second switch element is performed in response to said control signal applied to the second test pad through the first test probe.
 8. The method of claim 5, wherein the wafer further includes a third switch element coupling the first test pad to internal circuitry of the first integrated circuit die, the method further comprising: actuating the third switch element to cause the first test pad to be electrically connected to the internal circuitry; and applying the further test signal to or receiving the further test signal from the internal circuitry of the first integrated circuit die through the second test probe that is in contact with the first test pad.
 9. The method of claim 8, wherein the second test pad in the first integrated circuit die is further electrically coupled to a control terminal of the third switch element and wherein actuating the third switch element is performed in response to said control signal applied to the second test pad through the first test probe.
 10. The method of claim 9, wherein changing the first logic state of said control signal to the second logic state deactuates the third switch element and causes the first test pad to be electrically disconnected from the internal circuitry of the first integrated circuit die. 